An active-matrix display device displays a picture by selecting two-dimensionally arranged display elements row by row and writing a voltage to selected display elements in accordance with display data. To select display elements row by row, a shift register for sequentially shifting output signals in accordance with clock signals is used as a scanning signal line driving circuit. Alternatively, in a display device in which dot-sequential driving is carried out, a similar shift register is provided in a data signal line driving circuit.
In the case of a liquid crystal display device, a production process for forming TFTs (thin film transistors) in display elements may be used for forming a display element driving circuit integrally with display elements. In this case, it is preferable, for a reduction in production cost, that a driving circuit including a shift register be formed by transistors of the same conductivity type as those in the display elements. Further, an increase in the number of clock signals to be applied to the shift register results in an increase in area in which clock wires are laid out and an increase in power consumption. Against such a background, there has been a need for a shift register that operates in accordance with two-phase clock signals using transistors of the same conductivity type. Use of such a shift register causes a human eye to see a disturbance in a picture as generated when the power supply circuit of the liquid crystal display device has been turned on or off, with the result that the viewer experiences a feeling of discomfort.
Such a disturbance in a picture that is displayed on the screen can be alleviated by carrying out all-on operation by which when the power supply circuit has been turned on, the shift register is caused to output high-level output signals via all output terminals. A shift register capable of carrying out such all-on operation is disclosed, for example, in Patent Literature 1.
FIG. 35 is a block diagram showing a configuration of a shift register 110 of Patent Literature 1, and FIG. 36 is a circuit diagram of a unit circuit 111 contained in the shift register 110. Operation of the unit circuit 111 shown in FIG. 36 is described here. A plurality of unit circuits 111 contained in the shift register 110 each have all-on control terminals AON and AONB (negation of AON), and when the shift register 110 carries out all-on operation, each of the unit circuits 111 is supplied with all-on control signals AON and AONB from an outside source. When the all-on control signal AON is at a high level and the all-on control signal AONB is at a low level, the unit circuit 111 has its transistor T108 in an OFF state and its transistor T109 in an ON state. Assuming here that the shift register 110 is receiving a start pulse ST and clock signals CK1 and CK2 at a high level, the unit circuit 111 has its node N102 at a potential VSS and its node N101 at a potential VDD, thus outputting an output signal at the potential VDD via its output terminal OUT. Similarly, the other unit circuits simultaneously output output signals at VDD. Therefore, a shift register constituted by such unit circuits can carry out all-on operation.